macro_la.c,macro_la_tb_v.v,image.png
# caravel
j
macro_la.c,macro_la_tb_v.v,image.png
d
What is your user_project_wrapper output values on these ports: io_out[17:4] & io_out[0] + io_oeb[17:4] & io_oeb[0] ? as per your test case , these port should be drive with below values {io_out[17:4] , io_out[0] } = 15'b001000000010101; & {io_oeb[17:4], io_oeb[0] } = 15'h0;
j
After the simulation, the user_project_wrapper's outputs are io_out[17:4]&io_out[0] = 15'bz and io_oeb[17:4]&io_oeb[0]=0.
I'm using tri-state buffer outputs and so I'm turning off the tri-state using a signal named "active". It is expected, that when active is high, the io_oeb will be set to '0' and outputs will be assigned to io_out. But in my case, it's all set to z.
As you said, my logic is fine as I see the "Faulty ALU" and "Faulty Carry" printed correct which is what is expected, but the io_ports are not being driven with these values. {io_out[17:4] , io_out[0] } = 15'b001000000010101; & {io_oeb[17:4], io_oeb[0] } = 15'h0;. What and where could be the issue? Thank you.
d
You need to review your tri-state logic .. Is this design is in github ?
j
I have pushed the recent files. Thanks.
Files related to my macro will be: 1) verilog/rtl/macro_la.v 2) verilog/rtl/user_project_wrapper.v 3) verilog/rtl/alu_xor_4.v 4) verilog/rtl/properties.v 5) verilog/dv/macro_la/macro_la.c 6) verilog/dv/macro_la/macro_la_tb.v
@Matt Venn helped me figure out the issue. It was with the number of cycles the test ran. It was not long enough to set the IOs before which the testbench runs out of time and hence the outputs aren't written to the io_out.
Thank you very much for your immediate responses!