My gatelevel design seems to differ from the RTL d...
# openlanej
Jure Vreča
05/30/2022, 1:44 PMMy gatelevel design seems to differ from the RTL design. I am attaching an image from the exact same moment in simulation where the traces of the instruction and data ram are shown for both (data ram only has addr0 and din0). The CPU core is executing the program shown in the window, where the simulation waits for 0x6AB10000 to be written to dram. In RTL this seems to work fine, but gatelevel differs. Is there any reason why the gatelevel behavior would differ from the RTL?
a
Arman Avetisyan
05/30/2022, 2:07 PMYout picture is not very clear. Cant see any numbers
j
Jure Vreča
05/30/2022, 2:09 PMimage.png
Jure Vreča
05/30/2022, 2:10 PMimage.png
Jure Vreča
05/30/2022, 2:10 PMis this better?
a
Arman Avetisyan
05/30/2022, 2:10 PMSame. The numbers are very blurry
j
Jure Vreča
05/30/2022, 2:11 PMI can see them fine on my PC. Not sure what is going on
Jure Vreča
05/30/2022, 2:11 PMDid you try zooming in?
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Arman Avetisyan
05/30/2022, 2:11 PMHmm. Seems slack issue they are fine if downloaded
Arman Avetisyan
05/30/2022, 2:16 PMFirst I would check if you are viewing the nets you want to. I do not see what are these nets and to what they are attached
j
Jure Vreča
05/30/2022, 2:17 PMThese are the ports of the two sram macros
Jure Vreča
05/30/2022, 2:18 PMSince everything from processor core is flattened, synthesized and renamed I am having trouble finding any other appropriate nets. These nets however, since they are predefined macros, stay the same for both RTL and GL
Jure Vreča
05/31/2022, 6:39 AMIf anyone has a similar problem, I was able to solve this. The reason this was happening is because in my code somewhere I had a reg that was included in two always blocks. I picked up on this using by verilator as a linting tool.
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aryap
05/31/2022, 11:35 PMthis is always a good check, since synthesis tools and simulators tend to make different assumptions about loosely-specified verilog/behaviour
aryap
05/31/2022, 11:35 PMnice work