Has anyone experienced issues when trying to perform a simulation with components in the user project area that interface over the wishbone? Currently, my simulation halts after successfully performing the first write over the wishbone bus. Following that, no instructions make it to the processor. For what it's worth, I got the same effects when adding a value change over wishbone to line 82 in the example project .c source file of wb_port.

Late reply: This happens when the wishbone client is not working properly or you are trying to access an address to which your wishbone client does not respond to. If the first write "makes it", a possibility is that your wishbone client does not acknowledge correctly.