Finally, last workshop, last day - OpenFPGA Finally, we reach the end of the series - We have one final workshop to go - FPGA – Fabric, Design and Arch. Workshop registration closes on 15hrs and here's the registration link https://pages.razorpay.com/osfpga-fpga Overview In this workshop, we broadly cover 5 modules. The first module focuses on taking a digital design through Xilinx Vivado and programming it on the FPGA. We also demonstrate area, timing analysis, and post-implementation simulation. In the second module, we describe the OpenFPGA framework and demonstrate the VTR tool flow on two designs with an example architecture. Next, we repeat these tasks for a RISC-V based processor called RVMyth. We simulate RVMyth with a testbench through Vivado and program it on a Basys3 board. We then take it through the OpenFPGA framework through Skywater Open-source FPGA (SOFA). We also demonstrate area, timing analysis, and post-implementation simulation for the processor core after taking it through SOFA. Lastly, we summarize the area and timing results obtained by the design from Basys3 and VTR. All the best and happy learning