Hello! I don't know why but I encounter this error...
# sky130h
Harish Madhavan
05/29/2022, 1:48 PMHello! I don't know why but I encounter this error when I perform STA or floorplanning on yosys-generated netlist. I personally think that this is a parsing error; however, I am unsure about it. Has anyone encountered this issue and found a fix for it? Thank you for your patience.
k
Kauser Johar
05/29/2022, 2:00 PMCan you paste a few lines before and after the error? It might be the issue is somewhere else.
a
Arman Avetisyan
05/29/2022, 3:05 PMIt found a register declaration in your yosys generated verilog. Are you sure you properly generated the file?
Arman Avetisyan
05/29/2022, 3:06 PMJuat because you used yosys does not mean you have yosys netlist. Yosys need many transformations to create the netlist. The steps are defined by your yosys script.
Please post the content of the file.
Arman Avetisyan
05/29/2022, 3:07 PMIt is also weird that you are stopping on synthesis then doing sta/floorplan separatly. Why not use the openlane flow and let it do it automatically?
Post steps to reproduce the issue. From sources to scripts and commands run + logs.
Arman Avetisyan
05/29/2022, 3:12 PMI noticed that you posted your netlist below. Sta expects netlist, however you have rtl with a register declaration. How did you generate your netlist? it does not look like openlane generated
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Harish Madhavan
06/02/2022, 7:08 AM@Arman Avetisyan
Actually, yosys generated this netlist.
read_verilog <verilog file>
read_liberty <for each liberty file>
synth -top <top_module>
abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib -script +strash;scorr;ifraig;retime;{D};strash;dch,-f;map,-M,1,{D}
flatten
setundef -zero
clean -purge
rename -enumerate
stat
write_verilog -noattr <file_name>
Context: I have some analog blocks and a digital block which I have to synthesize. But the analog blocks can't be synthesized because "real" keyword is not a synthesizable construct. So, I had to create a separate .lib file for these analog blocks which I don't know how to include in the openlane flow and if I try copy-pasting the contents of the .lib file in the sky130 pdk, for some reason, it does not get recognized. So, I moved on and decided to use the individual tools (like Yosys) for getting access to "read_liberty" command. This is why I am not simply doing it automatically.
Harish Madhavan
06/02/2022, 7:09 AMI am still new to this. If I failed to consider something, please do tell me.
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Arman Avetisyan
06/02/2022, 7:13 AMThat's not the best approach. Here is the problems you are going to face:
1. You might not be able to generate a netlist with yosys because you missconfigured it. Which is exactly what issue you are having
2. You are going to waste a lot of time by fighting with the tools and flows. Again you are facing this issue right now
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Arman Avetisyan
06/02/2022, 7:18 AManalog blocks cant be synthesized, thats true. I dont understand what you are trying to do.
Are you trying to make a chip that has analog and digital blocks. It would make sense to use analog blocks for simulation purposes. But then why do you need a .lib?
So if you are doing simulation and dont have analog blocks why do you need openlane?
If you are trying to use openlane for analog circuit, then you simply cant do it.
✅ 1
Arman Avetisyan
06/02/2022, 7:23 AMThe flow would be:
1. simulation of mixed signal verilog that includes both digital components and analog ones. Purpose: validate that you sigital components work
2. Then implement the analog blocks GDS + Schematic
Use xschem + ngspice to make the components schematic.
Then magic vlsi and klayout to implement the gds of the component.
Pass drc, lvs, simulation with parasitics Generate lef and make .lib of the component
If you have digital components then use openlane with the analog blackboxea
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Harish Madhavan
06/04/2022, 2:04 PM@Arman Avetisyan Given GDS files for all three components individually, could you brief me how I can obtain the GDS for the entire soc using openlane?
Harish Madhavan
06/04/2022, 2:05 PMAgain, sorry if any of this seems too simple to be asked. I'm new to this.
a
Arman Avetisyan
06/04/2022, 6:19 PM1. Use magic vlsi to generate lef files.
Arman Avetisyan
06/04/2022, 6:19 PM2. (optional) make the .lib files or use .sdc to specify the driving cell for the pins
Arman Avetisyan
06/04/2022, 6:20 PM3. Use openlane with EXTRA_GDS and EXTRA_LEF parametrrs specified
Arman Avetisyan
06/04/2022, 6:22 PM4. Make verilog blackbox of your components. Refer to Yosys verilog blackbox documentation. Example: (*blackbox) module some_analog_module(); endmodule*
5. Design the top component. For simulation use the simulation models. For openlane, replace the analog modules with blackboxes
example file list for simulation:
top.v module1.simulation.v
example for openlane:
top.v module1.blackbox.v
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