@Mitch Bailey, @mehdi Hi Mitch, when I do the LVS check for my GDS, there are some problems, The MOSFETs having the same length can't be merged, attach my original Spice file, LVS extraction file, and the LVS report below, there are some MOSFETs have a big length value. What should I do to let the LVS pass? Thank you very much!

@Mitch Bailey and @Tim 'mithro' Ansell is there a repo where we can file issues for LVS (netgen)?

Yeah, it's about the stack variables which influence the GDS to generate, the magic will extract the GDS poly finger as a single MOSFET, but in GDS, these poly fingers just is seen as one MOS's length. attach my GDS below:

The repo for netgen issues is https://github.com/RTimothyEdwards/netgen Could you also post your netgen command? I believe the current netgen setup does not do reduction of mosfet in series. @Tim Edwards is that correct? With the

DCDC_CONV2TO2.spice

I don't think the following devices are correct. They are in both the

DCDC_XSW_NMOS

and

DCDC_XSW_PMOS

subcircuits. They have bulk (nwell) connections to

clk

and

clkb

but there is only one nwell in the layout.

x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2

Are these intended to act as capacitors? If so, just connect all the diffusion together. The size will be

w=2940000u l=150000u m=2

Also the size for these pmos

w=1260e-9

does match the extracted layout

w=1.26e+06u

x2 vOUT0 int_sw0 vIN VPB sky130_fd_pr__pfet_01v8 w=1260e-9 l=150000u m=2
x3 vOUT1 int_sw1 vIN VPB sky130_fd_pr__pfet_01v8 w=1260e-9 l=150000u m=2

@Jianwei Jia ^

Thank you @Mitch Bailey, let me check this problem.

@mehdi: There is also a slack channel #lvs .