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# magic
j
737f7db19552c72a1bc166e9709b9f0.png
m
Can you post your 2 LVS netlists (extracted and schematic generated) and your extracted netlist?
j
This is the original cdl file, extracted LVS cdl file, and LVS rpt.
BUFFER_lvs.rptBUFFER_lvsmag.spiceBUFFER.spice
t
@Jianwei Jia: My best guess is that you did not notice that the order of pins is different between the schematic and the layout. You can force the order of pins in the layout to match the schematic using the 
port index
command so that the extracted layout port order will always match the port order of the schematic. Otherwise you would have to adjust the call to BUFFER in your testbench.
@Mitch Bailey: Might be useful for netgen to have one additional diagnostic line noting whether the top level pin order is the same between the two netlists or not. . .
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m
@Jianwei Jia Sorry for the ambiguity. Can you post your PEX extracted netlist too (the one that is giving unexpected simulation results).
j
Hi @Mitch Bailey, this is PEX spice which has the wrong simulation.
BUFFER_pex.spice
@Tim Edwards, Hi Tim, yeah, I ignore it, let me check it again! Thank you!
@Mitch Bailey, @Tim Edwards, That does work! It's correct, I ignore the order of the pin, Thank you very much, Tim and Mitch!
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