open-source-silicon.dev

737f7db19552c72a1bc166e9709b9f0.png

Can you post your 2 LVS netlists (extracted and schematic generated) and your extracted netlist?

BUFFER_lvs.rpt

BUFFER_lvsmag.spice

BUFFER.spice

This is the original cdl file, extracted LVS cdl file, and LVS rpt.

<@U03839Z8D28>:  My best guess is that you did not notice that the order of pins is different between the schematic and the layout.  You can force the order of pins in the layout to match the schematic using the `port index` command so that the extracted layout port order will always match the port order of the schematic.  Otherwise you would have to adjust the call to BUFFER in your testbench.

<@U017X0NM2E7>:  Might be useful for netgen to have one additional diagnostic line noting whether the top level pin order is the same between the two netlists or not. . .

<@U03839Z8D28> Sorry for the ambiguity. Can you post your PEX extracted netlist too (the one that is giving unexpected simulation results).

BUFFER_pex.spice

Hi <@U017X0NM2E7>, this is PEX spice which has the wrong simulation.

<@U016EM8L91B>, Hi Tim, yeah, I ignore it, let me check it again! Thank you!

<@U017X0NM2E7>, <@U016EM8L91B>, That does work! It's correct, I ignore the order of the pin, Thank you very much, Tim and Mitch!