One of the VSD students @Geetima Kachari did SKY130 PDK timing analysis for all corners and has reported findings in the below GitHub link. Considering the fact that she is new to STA, the below work looks amazing https://github.com/Geetima2021/vsdpcvrd @Tim 'mithro' Ansell @Matt Venn @Tim Edwards @mkk @jeffdi @Nickson Jose @Praharsha you might want to take a look at this report

Nice diagrams. It looks odd that the fall delay increases with increasing gate size in tables 1 & 2.

@Geetima Kachari - can you take a look?

the table shows larger and larger pmos transistors connected to a fixed size nmos transistors. That makes rise times go down (the pmos can more easily pull the output up) while the fall times go up (the nmos has a harder time "fighting" the pmos to pull the signal down)

@Matt Liberty I had rechecked the values and it's correct. For my simulation I had kept my capacitor and input transition same and yes the pmos size increases with constant nmos size. Hence the capacitor takes more time to discharge as compared to charging the capacitor. Also you can find the programs in this repository https://github.com/Geetima2021/CMOS-Circuit-Design-and-SPICE-Simulation-using-SKY130-Technology. I have included the table for your reference.

are these actual cells in the sky130 library or is this some circuit you created for testing?

These are inverter circuits which we created for testing