@Tim Edwards, I've been experimenting with reducing the PDN to only a single power supply so I can get the PDN grid finer, so I can put more macros in the user space. This works, but then fails precheck because the gatelevel netlist only includes the first digital psu, which is mismatched with the 'golden ports'

Hack the gate level netlist to include the additional unused ports?

Hacking gate level netlist will not help, User gds XOR pre-checks expect 8 core ring. This is same issue raised in #openroad channel and also in openlane feature request : https://github.com/The-OpenROAD-Project/OpenLane/issues/1096#issue-1238025370 In MPW2/3/4/5 , I had some local hacks in script and source code to achieve this but this is not working MPW-6 due to new changes

probably worth opening an issue on the precheck as well then.

We've done it for MPW4 using slightly modified PDN script to generate core rings but no straps for unused supplies. Also gl netlist was patched a bit to add all supply ports. PDN script could be found here: https://github.com/egorxe/uranus_fpga/blob/main/impl/open/pdn_cfg.tcl , but it works only for older versions of OpenROAD with Tcl based PDN. Currently we are working for new script compatible with newer OpenROAD with C++ based PDN for MPW6. Also here is a quick and dirty shell script to patch supply inputs in verilog: https://github.com/egorxe/uranus_fpga/blob/main/impl/open/release_openmpw.sh