oh I've seem an answer to this on twitter by @Matt Venn (faster than I thought!) "there are a few ways to simulate at a lower level, we have gate level and transistor level. Both useful, but I typically only use GL [gate level] for chip verification. Transistor level more for learning and experimentation", maybe this thread is a better place to discuss. So how to simulate the design at transistor level? by gate level we are talking about verilator or some other tool? I plan to do a development to couple some graphics output to the simulator to really see how the chip is behaving, similarly as I did graphics output coupled to verilog simulation