https://open-source-silicon.dev logo
Join Slack
Powered by
Hi all! In want to know how I can simulate a desig...
# general
s
Hi all! In want to know how I can simulate a design at the gate or transistor level, so to check there are no hold time violations or other issues that can appear after tape out
✅ 1
m
You can dump a gate level path with sta's write_path_spice. Beyond that you would need to setup a simulator and the transistor netlist for the standard cells.
s
I'm interested on that, I need to dig into the many tools that would be easier since the tutorial. I'll be glad about a similar one focused on simulation. I'd feel a bit hesitant to submit a project that wasnt simulated at the lowest practical level (maybe not transistor)
I wounder if using simulators would detect años show problems as the one regarding the hold violations... Will it be possible for example to misconfigure something and so make the simulation not pass? Similarly as what we do with verilator but at a lower level. I believe hay having a working simulation provides more peace of mine that having a tool that just checks if the constraints are met
m
If you simulate a path with a large hold violation you should see the failure in your simulator
s
Good! What simulator are we talking about? At what stage of the workflow?
m
I don't know what people are using for spice type simulator. Probably xyce. @Matt Venn is that what OL recommends?
s
Do we know if we can simulate let's say a CPU core at such lower level? Spice are for analog simulation
m
you won't want to simulate a whole core, it will be too slow. That's why I suggested write_spice_path which will just write a critical path
s
I see that as a good shorcut, but isn't it possible to simulate a design such as riscv CPU, at any lower level than verilator, in a practical fashion?
m
not really
s
I see to make that possible will be quite useful, what's the roadblock?
m
Hi @suarezvictor welcome to the slack, great to see your enthusiasm, ¡bienvenido!
@Matt Liberty thanks for answering all the qs
I don't know about a recommended simulator, just started asking about #xyce myself
@suarezvictor it's Friday night here so I wont be answering many questions , and I'm just learning this stuff myself at the moment
We want to avoid simulating the whole chip at the lowest level because it's too long as matt says
Thats why people like @Tom Spyrou developed static timing tools
We had hold violations in mpw1 due to tool misconfiguration/ first time issues
But the idea is to trust the sta tools to catch hold violations and then try to optimise digital simulation to be as fast as possible
I'm currently trying to learn how to do mixed signal verification, and one reason it's hard is because analog is so slow
Buen fin de semana a todos!
s
Yes I definitely know analog simulation is slow
Maybe impractical
But I think any newcomers like me would benefit of seeing the design work for learning and to be sure it will work as we ser it working in simulation
I bet that simulating at least a 7-segment decoder would be quite instructive
Or why not a simple pong game as the original hardware-only one
And that would be much better than no simulation
m
Maybe this will help you get started: https://github.com/mattvenn/simulate-gate/tree/nand
💯 1
m
For very small designs simulation will be possible depending on your patience
s
I'd have los of patiece, for example let's assume you send to tape out a design each 6 months, I think you can spend a week doing low level simulation, even if you need to simulate separate parts of the design
This seems excellent! Do you have any guess of how many gates I can simulate let's say in day? 10, 100, 1000?
Let's imagine a cost aproach to the issue, and assume there's a way to distribute the simulation among many processors: how large a design we can simulate spending $500 on cloud processing services? Maybe that many CPU can taclke the problem
2 Views
Open in Slack
PreviousNext
Powered by