open-source-silicon.dev

Hi, I'm doing LVS of a circuit that contains digital cells using netgen.
I'm getting results that look like the following:

`Net: Clk_out0                              |Net: clk_out0`                              
  `sky130_fd_sc_hs__dfrbp_1/2 = 1           |  sky130_fd_sc_hs__dfrbp_1/D = 1`           
  `sky130_fd_sc_hs__dfrbp_1/8 = 1           |  sky130_fd_sc_hs__dfrbp_1/Q = 1`           

On the left is the netlist generated by xschen on the right the one generated by magic. One can see that that in the layout the ports of the digital cell have names while xschem outputs numbers.

What is the best way to make them match? One option is probably to change the labels in the layout. Can netgen be configured to match labels and numbers?

It turdend out I had to include the spice file containing the logic files in xschem. `.include /usr/local/share/pdk/sky130B/libs.ref/sky130_fd_sc_hs/spice/sky130_fd_sc_hs.spice`  Now LVS works great!