Hi , How to check if my substrate tapping is correct or not ? I tapped pmos and nmos with respective taps and DRC full is clean . But when i extract to spice , i still see VSUBS being printed in the spice netlist ; Shouldnt we expect GND ? Steps : extract all ; ext2spice hierarchy on ; ext2spice Xand2_g5D10_1 and2_g5D10_2/VDD OUT1 IN0 inverter_d5g10_W1um_L0p420_0/OUT VSS VDD VSUBS + and2_g5D10 Xand2_g5D10_2 and2_g5D10_2/VDD OUT2 IN1 inverter_d5g10_W1um_L0p420_1/OUT VSS VDD VSUBS + and2_g5D10 Thanks

Can you post your full extracted netlist or is it to large?

attached

Are you extracting for LVS or simulation? If you're extracting for LVS, be sure to set the

lvs

option first.

ext2spice lvs
ext2spice

Do you have pins on the top level? The VSUBS lower level nets appear to be connected correctly at the top level, which is what is expected if you have your substrate taps at the top level.