<@U016EM8L91B> Do you have any suggestions about u...
# magic
y
@Tim Edwards Do you have any suggestions about using obstructions in the lef file? Our capacitor cell used m4 & m5, which are exactly the same as the power rail layers that would lead to drcs (as shown below). I'm trying to write OBS in lef to exclude the whole box area (except pins for sure). Here are two styles I tried so far. While both ways didn't work, if I check that in magic use
see no
and
see obsm4
, I would see no obstruction layers still and the drc would persist. 1.
Copy code
OBS
  LAYER obsm4 ;
    RECT 94.00 -36.00 3687.00 963.00 ;
  LAYER obsm5 ;
    RECT 94.00 -36.00 3687.00 963.00 ;
END
2.
Copy code
OBS
  LAYER m4 ;
    RECT 94.00 -36.00 3687.00 963.00 ;
  LAYER m5 ;
    RECT 94.00 -36.00 3687.00 963.00 ;
END
t
(2) is correct. These are not magic layer names in the LEF file; they are names determined by the technology LEF file. You would use the normal layer name inside an OBS block to declare an obstruction. But normally you should not be writing LEF files yourself. Typically what you do is to create the layout, and then generate an abstract view from the layout (in magic,
lef write
or
lef write -hide
depending on the style of the abstract view you want).
2
y
Thanks, while do you know how to create obstructions in magic? Maybe box and then paint obsxxx? My writing style 2 in the lef file didn't work so far if I put this cell into innovus to the PnR
@Tim Edwards I'm sorry to ask you about this again, while my (2) didn't work, after I inserting that in my lef file, the power rail still overlap with the obstruction. Do you know how to manually write obstructions and view obstructions in magic instead of in the lef file?
t
When reading LEF files, magic maps the obstructions to layers "obsli", "obsm1", "obsm2", as you guessed. Because these layers look just like regular metal layers, I "locked" them so they don't appear in the layer icons in magic, and you can't draw them by default. To do that, you need to use the command
tech unlock *
to access these "locked" layers.
y
Get it. Tim, thanks for suggesting the hidden functions lol
a
Hi @Yueting Li @Tim Edwards, with adding obs layers through magic, were you able to successfully integrate capacitor layouts using openlane (I am assuming you needed OBS in the LEF to prevent PDN from routing over the caps). I am trying this now and running into congestion trouble (presumably because OBS and M4/M5 overlap now for us but trying to confirm)
y
I did it. While I was always using innovus and haven't tried openlane yet
👍 1
a
Oh cool! Thanks for the quick reply. I'll continue chasing this in the openlane channel then, thanks!
💪 1
Hi @Tim Edwards, I see that adding and then removing obsm4,obsm5 seems to introduce DRC errors (looks like it takes some vias along with it) -- is this a known issue with manually painting obs with magic?
Hi @Tim Edwards, I tried making a simple test case with m4 and m5 and a via in between: (A) Before adding obsm4,obsm5: the two metal lines short through the via as expected (B) After adding obsm4,obsm5: the metal lines seem to be disconnected now (C) Going back to seeing no obsm4,obsm5 still appears to show a disconnect through the via
t
I'm confused about how your are using obstruction layers. Obstruction layers only exist in abstract views and indicate places where there is metal in the actual layout for that cell that does not belong to any pin. The purpose is to prevent routing tools from routing near or over the obstruction area and making a short to something inside the cell. So if you have an obstruction in your abstract view, you should not be placing anything over or near it in the parent cell.
a
Thanks @Tim Edwards, yes I might be doing something wrong. I am trying to integrate analog cells with digital macros synthesized using openlane. One way to do this seemed to be to use a blackbox'd verilog alongwith the analog cell's LEF/GDS, and have openlane place and stitch the analog cell with a digital macro. But I was running into trouble with openlane's PDNgen, which would try to route M4/M5 power strips over the analog cells (which is a problem since I have mimcaps using M4/M5 as signal and ground layers). The goal of adding OBS in magic was to export these to LEF, so openlane could keep out of these areas. But I am not sure if I am painting my OBS correctly -- because doing it seems to introduce DRC errors, possibly by some unwanted interaction between OBS layers and some via layers? This is what I was trying to capture with the small test case above. I was thinking if I had an M4 trace with a via to an M5 trace, adding OBS paint on top shouldn't affect the connectivity, but it looks like it does. What is the recommended way for doing this? (Aside, I updated to the latest openlane and made my analog macro bigger, and these two factors are somehow working together now and preventing PDNgen from shorting into the analog cell, so I might not need to add OBS manually after all.)
t
What you should do is (1) make sure all pins in the analog block reach the edge of the bounding box (or close to it), and (2) use "lef write -hide" to get an abstract view that exposes the pins but fills the entire rest of the area of the analog block with obstruction layers. That should be sufficient to make sure that the tools will route to the block without routing over it.
1
a
lef write -hide
is giving comparable behavior to manually painting OBS -- this is great, thanks!