@User: @User and me are wondering if there is a way to do a v2lvs with netgen?

@User Yes! @User has a flow which converts verilog to spice and then combines with existing low level spice files which is how Calibre does things, I believe. However, there is also an option to openlane's

flow.tcl

that combines the verilog and spice to do device level LVS.

flow.tcl -design <my_design> -lvs -gds <gds_file> -net <top_gate_level_verilog>

This runs magic extract and netgen in the openlane directory structure. You will need to add non-default spice libraries (if used) and other verilog files to the config.tcl. For example, in order to run gate level LVS on

mgmt_core_wrapper

, add the following:

set ::env(LVS_EXTRA_GATE_LEVEL_VERILOG) "
      $script_dir/../../verilog/gl/mgmt_core.v
      $script_dir/../../verilog/gl/DFFRAM.v"

set ::env(LVS_EXTRA_STD_CELL_LIBRARY) "
        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/spice/sky130_sram_2kbyte_1rw1r_32x512_8.spice"

Let me know if things don't work as expected. There may be a few programs you need to tweak.

Thanks @User, I will checkout openlane for the details.

@User Tanks so much! what we are trying to do is get spice out of synthesis to run simulations. Our block is mixed signals and cannot run through openlane as it is. Do you know the cmd used to generate the spice out of synth verilog? is it the

write_cdl

cmd from openroad?

Do you have gate level powered verilog? If you do, you don't need to convert it to spice to run LVS. Also, the config.tcl file for the LVS option is only used for creating the directory structure. There's no routing, etc.

@User we aren't trying to run LVS . The goal is to run a spice simulation out of synthesis. Our repo is here: We have an LVS issue for the temp sensor and we are currently adding the dcdc converter: https://github.com/idea-fasoc/OpenFASOC/tree/main/generators Your inputs would be really helpful here.

So you want to run spice simulation on a converted verilog netlist?

correct 🙂

@User I cloned the repo but couldn't find a gds or verilog for a temp sensor. Not really willing to debug installing the generator and associated programs. If you have a gds and verilog files that aren't passing LVS, you could tarball them to me and I'll take a look.

sure will do! @User can you please do that for the tempsensor?

Sure thing, one moment

Looks like your metal5 power grid is on layer 13/0 instead of 72/20 and metal4 is on layer 11/0 instead of 71/20. Maybe there's some mixup in the process specification?

Oops. There were some issues with the old tool setup. I have just updated them and generated the results again. Please see the new tar ball. Thanks!

The only error I see is that r_VIN and VIN are the same net in the layout.

Subcircuit summary:
Circuit 1: tempsenseInst_error             |Circuit 2: tempsenseInst_error
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_03v3_nvt (56)           |sky130_fd_pr__nfet_03v3_nvt (56)
sky130_fd_sc_hd__decap_4 (106->2)          |sky130_fd_sc_hd__decap_4 (106->2)
sky130_fd_sc_hd__or3_1 (1)                 |sky130_fd_sc_hd__or3_1 (1)
sky130_fd_pr__nfet_01v8 (56)               |sky130_fd_pr__nfet_01v8 (56)
sky130_fd_pr__pfet_01v8_hvt (61->60)       |sky130_fd_pr__pfet_01v8_hvt (61->60)
sky130_fd_sc_hd__nor3_1 (21)               |sky130_fd_sc_hd__nor3_1 (21)
sky130_fd_sc_hd__dfrtp_1 (4)               |sky130_fd_sc_hd__dfrtp_1 (4)
sky130_fd_sc_hd__a221oi_4 (1)              |sky130_fd_sc_hd__a221oi_4 (1)
sky130_fd_sc_hd__nor2_1 (1)                |sky130_fd_sc_hd__nor2_1 (1)
sky130_fd_sc_hd__or2b_1 (1)                |sky130_fd_sc_hd__or2b_1 (1)
sky130_fd_sc_hd__mux4_1 (1)                |sky130_fd_sc_hd__mux4_1 (1)
sky130_fd_sc_hd__nor3_2 (4)                |sky130_fd_sc_hd__nor3_2 (4)
sky130_fd_sc_hd__nand3b_1 (2)              |sky130_fd_sc_hd__nand3b_1 (2)
sky130_fd_sc_hd__or3b_2 (1)                |sky130_fd_sc_hd__or3b_2 (1)
sky130_fd_sc_hd__o2111a_2 (1)              |sky130_fd_sc_hd__o2111a_2 (1)
sky130_fd_sc_hd__dfrtn_1 (43)              |sky130_fd_sc_hd__dfrtn_1 (43)
sky130_fd_pr__nfet_01v8_lvt (20->2)        |sky130_fd_pr__nfet_01v8_lvt (20->2)
sky130_fd_sc_hd__o211a_1 (2)               |sky130_fd_sc_hd__o211a_1 (2)
sky130_fd_sc_hd__conb_1 (1)                |sky130_fd_sc_hd__conb_1 (1)
sky130_fd_sc_hd__mux4_2 (1)                |sky130_fd_sc_hd__mux4_2 (1)
sky130_fd_sc_hd__nand2_1 (3)               |sky130_fd_sc_hd__nand2_1 (3)
sky130_fd_sc_hd__or2_2 (1)                 |sky130_fd_sc_hd__or2_2 (1)
sky130_fd_sc_hd__o311a_1 (1)               |sky130_fd_sc_hd__o311a_1 (1)
sky130_fd_sc_hd__o221ai_1 (1)              |sky130_fd_sc_hd__o221ai_1 (1)
Number of devices: 267                     |Number of devices: 267
Number of nets: 169 **Mismatch**           |Number of nets: 170 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: tempsenseInst_error             |Circuit 2: tempsenseInst_error

---------------------------------------------------------------------------------------
Net: r_VIN                                 |Net: r_VIN
  sky130_fd_pr__nfet_03v3_nvt/3 = 14       |  sky130_fd_pr__nfet_03v3_nvt/3 = 14
  sky130_fd_pr__nfet_03v3_nvt/1 = 14       |  sky130_fd_pr__nfet_03v3_nvt/1 = 14
  sky130_fd_pr__pfet_01v8_hvt/(1|3) = 9    |
  sky130_fd_pr__pfet_01v8_hvt/4 = 9        |
  sky130_fd_sc_hd__decap_4/VPB = 1         |
  sky130_fd_sc_hd__decap_4/VPWR = 1        |
  sky130_fd_sc_hd__nand2_1/VPB = 1         |
  sky130_fd_sc_hd__nand2_1/VPWR = 1        |
                                           |
(no matching net)                          |Net: VIN
                                           |  sky130_fd_sc_hd__decap_4/VPB = 1
                                           |  sky130_fd_sc_hd__decap_4/VPWR = 1
                                           |  sky130_fd_pr__pfet_01v8_hvt/(1|3) = 9
                                           |  sky130_fd_pr__pfet_01v8_hvt/4 = 9
                                           |  sky130_fd_sc_hd__nand2_1/VPB = 1
                                           |  sky130_fd_sc_hd__nand2_1/VPWR = 1
---------------------------------------------------------------------------------------

that's because we are connecting a Header (switch output) to the 2nd voltage domain's VDD (IE VIN)

The CDL has 2 separate nets,

r_VIN

and

VIN

. The layout has both texts at the same location on the same layer, so only one gets extracted. If they're supposed to be the same net, the CDL needs to be changed so that these are connected.

@User Can you please check this. Thanks @User