I am having a LVS failure with two unmatched pin around power .. Any suggestion how to fix this File: 26-user_project_wrapper.lvs.lef.log LVS reports: net count difference = 0 device count difference = 0 unmatched nets = 0 unmatched devices = 0 unmatched pins = 2 property failures = 0 Total errors = 2 File : 26-user_project_wrapper.lef.log shows below error saying Power pins are different .. Subcircuit pins: Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper -------------------------------------------|------------------------------------------- vssd1_uq9 |vssd1 Mismatch vccd1_uq26 |vccd1 Mismatch In GDS review wise: Power hook looks to good from Core Ring to Hard Macro

1. Which openlane? 2. How this pins are configured? From the looks of it, you have multiple vccd/vssd and names suggest you use a def template for this 3. Power "pins" like vccd vssd should not be in the output as they are generated in the form of power rails and rings, not "pins".

I am using Latest MPW-5 openlane.. Pad position are as per cavavel configuration .. My project Tape-out pre-check passes .

Precheck does not check lvs. You layout does not match your rtl because lvs fails. You need to debug why, because if you send it to tapeout, it basiclly wont work.

@User Looks like you have 2 separate vssd1 nets and 2 separate vccd1 nets in your layout. magic extracts unconnected nets with the same label by adding the '_uq#' suffix to one of the pin names. In an ideal LVS flow, these unique nets will connect at the next hierarchy and the design will match at the top level. We're not quite able to do that with caravel now. One solution is to physically connect the separated nets at the user_project_wrapper level.

@User Do see this issue created during PDN network generation? Not sure why PDN flows not shown any error ..

Looks like you're doing lef based LVS. Have you tried GDS based LVS?

I don't see any config setting for LVS for LEF/GDS .. For DRC there is option set ::env(MAGIC_DRC_USE_GDS) {1}