<@U01L8BR7FFA> thanks - keep me posted on progress...
# reram
j
@User thanks - keep me posted on progress. that may be possibe.
👍 1
g
Hello @User Simple rerun of _caravel_user_project_analog_ is also failing https://github.com/ganeshgore/caravel_user_project_analog/tree/ci_test
Other than that testchip_4t1r just has design verification related errors, DRC is already clean