Hi, just want to give a bit further info about our rram_testchip. We will share more details later once we properly document it. Basically, we aim to use rram cells (replacing the latches) for the configuration bits. For the test purpose, we put couple of test circuits including rram-based pass gate (mPG), the NanoBridge-like rram cells (voltage divider) and the control/program circuits, those are made as custom cells for the digital implementation flow. Those test circuits have both pros and cons, for example, the mPG requires a refresh cycle after 0.4ms or the cross current in the voltage divider is not ideal for a large scale design and so on. Below are some figures of the test circuits for your reference and the mPG paper: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9401603

@User have you checked this?

Thank you @mehdi