Hello all, I have been trying to build the ReRAM xyce plugin using the Buildxyceplugin tool but unfortunately am getting this error. Could somebody point out the mistake?

[fatal..] ../../cells/reram_cell/sky130_fd_pr_reram__reram_cell.va: during lexical analysis syntax error at line 54 -- see '='

That is probably a question for Eric Keiter in the #xyce channel. But also, Eric mentioned this group as an appropriate place for the Verilog-AMS model discussion: https://groups.google.com/g/xyce-users/.