Hi, @User, thank you for adding me. I was lagging behind, i have started reading the sky130_fd_pr_reram docs and the rram_testchip repo. What is the goal with ReRAM cells? creating an array with 1T1R topology? 1 bit / cell ? may be it will be used to configure programmable array of gates?

Yes, that's exactly right, although since ReRAM has two resistance values which are both mid-range, I think the memory cell is a bit more complicated than 1T1R. It is going to be available on every MPW run starting with MPW-4 (which already went to production). There is at least one design with ReRAM on MPW-4 and several slated for MPW-5. There is a Verilog-AMS model

<http://sky130_fd_pr_reram__reram_cell.va|sky130_fd_pr_reram__reram_cell.va>

which is easy enough (I think) to incorporate into Xyce but not so good for ngspice. We really need to put pressure on the ngspice developers to enable a plug-in model for shared object libraries instead of requiring that ngspice itself be recompiled every time an AMS model is needed. Or maybe we can work up a decent SPICE model with standard components.

Thank you for the clarifications. Yes a spice model with standard components (using Bsources and/or variable valued resistors) can be done, we have done that many times for various non volatile memory cells, including flashes and various snap-back kind of memristors. The problem is if the foundry characterization data goes into the verilog-A model this is at the end what designers want to simulate their designs with.

Hi @Stefan Schippers @Tim Edwards I just reran open_pdks to get the sky130B installation done. My sky130-pdk libraries do show sky130_fd_pr_reram now, but the xschem_sky130 directory doesn’t appear to have any associated symbols for this library. Have any symbols been made? If not I can try calling the reram spice files directly within xschem, thanks!

Hi, @Abhinav Uppal, thank you for bringing up this issue. I can easily add 130B (reram) symbols. Will look into the docs. Do you have a list of hi-priority devices to work with?

Thank you! No, I am just getting started with reram so anything works, thanks!

Hi, @User, have you added the symbols for reram in 130B? Actually, I am unable to see in the repo skywater-pdk-libs-sky130_fd_pr_reram/cells/reram_cell/

Yes, the ReRAM symbol is in the xschem installation for sky130B.

@Bhanprakash Goswami as @Tim Edwards said there is a symbol for the reram and it produces a spice netlist according to this example. I have not yet tried to simulate this as it is based (IIRC) on a verilog-AMS model that is not trivial to simulate with ngspice. If someone with some experience wants to help, that would be great!.

Specifically, ngspice does not have a "plug-in" capability like Xyce does, so while it supports Verilog-AMS, any such model has to be dropped into the ngspice source code, and ngspice has to be recompiled with it, such that you end up with a PDK-specific version of the ngspice executable. For Xyce, the Verilog-AMS model needs to be compiled, but then is a standalone shared-object library that can be loaded into Xyce at run-time. I have not had the opportunity to try any of these methods.

Thanks, I will check.