@User this is impressive!! i created the reram symbol with no tests at all, as i am not very experienced with Verilog-A. I will learn from your example. I see you post-processed the xyce generated raw file with ngspice, what is the reason? was xschem unable to read the original raw file? thanks.

Thanks 😀. The original raw file was readable, but I wanted to change the x axis to be the voltage and not the time (and also change the name of the trace for the device current to something more readable).

@User it is possible to change the x-axis in xschem graphs, although it is not directly shown in the graph edit dialog box (will add this soon), select the graph by clicking with the mouse the internal area , very close to the border (left/right/bottom), then press 'q' as usual for editing object attributes, set the 'sweep' attribute. In example below i am plotting voltage A vs Z and Z vs A:

Thanks! I did not know about these options. I haved updated the example :) BTW, how do you open this graphdialog? Another thing, I am using xyce without the -r flag and instead have the print command output all the voltages and currents to the raw file, otherwise I doesn't save the current for the ReRAM (just for the voltage source, I guess since it is just the opposite direction)

The graphdialog is opened by double-clicking in the center of the graph. By default (with -r) i believe Xyce saves all node voltages and voltage source currents (the primary unknowns that solve the whole circuit). Even with -r option may be there is some instruction to save additional variables, like similar

.save all

and

.options savecurrents

in ngspice. Note also that you can graph expressions in xschem, using simple RPN notation ( so (a+b)*c is input as a b + c *): so for example graphing the negation of a voltage you simply do

"0 v(a) -"

or

"v(a) -1 *"

This is great! I have updated to example to be compatible with -r output. Notice that I use a simple script called XyceLP.sh for the xyce simulation. It should be installed in the xyce /bin folder and it loads the .so files from xyce /lib/plugins as xyce plugins. This is where I put the reram plugin.

@User: What are the steps I would need to take to compile the

.so

file for Xyce for the ReRAM (also for the varactor, as I am using an old SPICE model because the newer model is Verilog-A)? I would like to have open_pdks compile and install the plugin into the PDK automatically.

@User Interesting. To compile you need xyce compiled with the shareable flags and admsXml installed. Then, xyce is installed with a script to build the plugin. I will try to add a Makefile for this. Also notice that I changed the VerilogA module a bit to make it work.

@User: Yes, those are precisely the things I need to know to integrate a working model into open_pdks.