jeffdi
caravel
do a git pull
2. Update OpenLane — run make openlane
from the project root
3. Update the PDK — run make pdk
from the project root
4. Create an SDC file if you do not already have one at openlane/<macro-name>/base.sdc. You can use the following file - just define CLOCK_PORT and CLOCK_PERIOD at the top of the file.
set ::env(CLOCK_PERIOD) <clock-period>
set ::env(CLOCK_PORT) <clock-port-name>
set ::env(IO_PCT) 0.2
set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
set ::env(SYNTH_CAP_LOAD) "33.5"
set ::env(SYNTH_MAX_FANOUT) "4"
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set_propagated_clock [get_clocks $::env(CLOCK_PORT)]
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
puts "\[INFO\]: Setting input delay to: $input_delay_value"
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]
Finally, run timing with the following commands from the project root…
export OPENLANE_ROOT=<openlane-root>
export CARAVEL_ROOT=$(pwd)/caravel
make rcx-<macro-name>
******************************************************************Matt Venn
10/27/2021, 7:29 AMMatt Venn
10/27/2021, 7:30 AMMatt Venn
10/27/2021, 7:30 AMMatt Venn
10/27/2021, 7:33 AMMatt Venn
10/27/2021, 7:38 AMMatt Venn
10/27/2021, 7:38 AMMatt Venn
10/27/2021, 7:39 AMMatt Venn
10/27/2021, 7:39 AMjeffdi
jeffdi
base.sdc
example file above