On some test I was getting HOLD violations on input ports from the logic analyzer. Those violations happened with the default base.sdc that uses

sky130_fd_sc_hd__inv_1

as

SYNTH_DRIVING_CELL

. If I change the driving cell

sky130_fd_sc_hd__inv_8

those hold violations disappear. I was wondering if that was ok. I looked at the caravel harness and it seems to be using inv_8 cells on its output to the user project area (

mgmt_protect

), so I guess it's fine?

The

inv_8

cell has the same function as

inv_1

, but it has higher drive strength so it improves cell delay. It also takes more space on the die. Replacing a cell with a higher sized version is a good way to fix timing violations.

If this is just in the sdc constraints, it isn't actually adding the cell just using it to model the input slew/delay.

right, just in the sdc constraints. If caravel is feeding the user project LA ports through inv_8 cells I could make that change on the constraints file and I wouldn't be cheating, right?