One thing I noticed is that the

mgmt_core

clock tree last cells, before the leafs, is a clkbuf_1 that drive in some cases 12 leafs (clkbuf_16). That seem to be adding some big delays on my logs.

That seems strange - how is the clock tree being generated? Have you tried repair_clock_nets ?

This is the clock tree from the efabless caravel mpw-3a (https://github.com/efabless/caravel) repository, I didn't generate it. I still don't know if this is the right repository to use for this tests or not

@User @User is mpw-3a using caravel or caravel_openframe?

given that this is a critical part of the way caravel works, and many projects use the wishbone bus, it would be great to get a bit more support on helping us check for timing issues. @User @User

I have also tried to do full-chip STA including all the caraval blocks and observing similar HOLD violation inside

mgmt_core

as observed by @User I have bit confused on the latest database available in caravel repo. Most of the def's looks to be more than 3 to 6 Month Old .. Not sure if they are latest one. Can any one from caravel team can confirm if these def's are latest tape-in quality one: https://github.com/efabless/caravel/tree/master/def

I believe that caravel_openframe is the replacement for prior caravel that had hold issues. I was just hoping for official confirmation. You might try testing with that instead.

@User In https://github.com/efabless/caravel_openframe I don't see "mgmt_core_wrapper & mgmt_core" .v/.def/.lef/.gds file in the repo .. Not sure these are missed out in check-in ? As per caravel.v there is module instantiation mgmt_core_wrapper soc (

see https://github.com/efabless/caravel_pico

Thanks. I'm going try with with those

@User @User I see chip_io.def is missing in this folder : In https://github.com/efabless/caravel_openframe But i am able to see chip_io.lef/chip_io.spef/chip_io.gds files

The IOs are probably custom logic and don't have a def.

@User for running the opensta timing reports you just need the verilog and spef files I think you need the DEF if you want to create the SPEF, but they are already there

@User @User Did you reviewed these unconstrained report during STA? I see some of the FF are not getting clock .. May be need addition clock definition

@User how did you get that report? I'm running STA with

make caravel_timing

and didn't see that

@User I'm not part of the caravel team, I'm just trying to give what help I can

@User You need to add "check_setup -verbose > unconstraints.rpt" in the make caravel_timing call to check any missing constraints. Based on the caravel netlist review i have added following clocks in sdc create_clock [get_pins housekeeping/_8847_/X ] -name "csclk" -period 25 create_clock [get_pins clocking/pll_clk ] -name "pll_clk" -period 25 create_clock [get_pins clocking/pll_clk90 ] -name "pll_clk90" -period 25 Which reduced some of the unconstrained .. But it's better SDC get updated from Caravel team ..

@User @User @User My apologies for the delayed response Let me shed some light. First the caravel is still a moving target and we are about to update Caravel repo to reflect all the updates. We could use your diligent eye and effort to dig into the following two repos. The make files for those repos contain targets for running the timing analysis and design verification test benches. The repo containing the mgmt_core_wrapper https://github.com/efabless/caravel_mgmt_soc_litex The repo containing everything else but the mgmt_core_wrapper. https://github.com/efabless/caravel_openframe Keep in mind that the names of these repos are likely going to change to be consistent with previous naming conventions. This structure became a new requirement by google for future MPW runs. It will provide google with the flexibility to change the management CPU into different ones that are supported by Litex.

@User MPW-3 is going to use this new version of caravel, right?

yes

@User this new version of caravel is using the Litex VexRiscV core instead of PicoRV-32?

I believe that is correct but mkk can confirm

yes

@User @User Is there is plan to clean up caravel sdc in https://github.com/efabless/caravel_openframe, Currently in see only one clock is defined in sdc. As per un-constraint reports I see there are missing clock constraints. Attached the un constraint report.