Hi Mehdi, how are You ? I hope You are doing well keeping pace to meet Your deadlines. I would like to comment You some advances: 1. I put the module on diet and was able to reduce it size significantly (more than twice). The outcome was that I have manage to place 15 channels on the left side of the user project area. 2. The design itself does not have multiples clock domains. In general I use 24 MHz clk from wb_clk_i and derive some auxiliary syncronizing signals: (a) a 50% duty cycle 4.8 MHz clock for the microphones outside the chip, (b) a 4.8 MHz CE signal for the PDM demodulator, (c) a 480 kHz CE for PCM data path. The above implies some advanced techniques in during STA analysis like incorporation of generated_clocks and multi cycle path analysis. I have some ideas on that however I would like to discuss it with somebody. 3 Continuing the issue of STA, the design reports some hold and setup violations. I got the setup violations when I have replicated the channels, what is not a surprise because of increased load on the buses. Nevertheless I would like to consult, how to deal with the issue during the flow. I do not know if one can insert some delay buffers (hold violations) or high drive buffers (setup violations) manually or there are other techniques to fix the violations. 4. I have generated the macro of one channel configuring the pin orientation in such order that the WB bus can be routed in the center of the chip, and the input points towards the IO pads. My goal is to put second column of 15 channels however in order to do that I need to mirror the inputs/outputs horizontally. Is there way to do that or I have to generate other macro ? I hope You will find some time to help. If not would You be so kind and contact me with some specialist in STA, which seems to be the biggest issue right now.

@Krzysztof Herman Here are a few comments: 1. How did you manage to do that? architectural changes or yosys/abc recipes? 2. I am not fully understanding. Is your chip only supporting 1 clock (24MHz)? I think the answer is yes. Then how is the communication to the outside of the chip? is it synchronous to external signals? I would recommend making it async. and use some kind of handshake protocol -- Please ask others as well 3. Did you have a look at ORFS? OpenLANE is updating there cmds and flow to help fixing the timing. I can try and have a call to discuss this in more details. 4. You can change the macro placement (mirroring or rotation) in the placement config file. Have you tried that?

Hi Mehdi, thanks for Your replies. Lets continue: 1. All changes were made on the architectural level mainly using resours sharing during DSP operation. 2. Let me provide some more information. So, in our IP we derive 24 MHz clock from the Caravel SoC (the 24 MHz can be set using 8 MHz cristal and some custom PLL settings). The uniique device we are going to connect to the physical chip is a digital microphone, which requires a 4.8 Mhz, 50% DC clock and it provides a 1 bit PDM signal. In fact we will connect multiples microphones, one per each channel. On each channel we demodulate the PDM signal at 4.8 pace and process the demodulated sigan at the pace3 480 kHz (thus decimating 10 times the PDM signal). In order to perform the above we generate: (1) a 4.8 MHz 50 % duty cycle clock signal for the microphones and bond it to the io_out[0], (2) generate clocke enable signal ce_pdm for the PDM demodulator, (3) generate clocke enable signal ce_pcm for the datapath which process the samples at the pace of 480 kHz, All the above signals are synchronous and derived from the main wb_clk_i clock signal of 24 Mhz. The main issue is to write correct constrains for the STA. Since I use clock enables it implies multiccycle paths. Simply I would like to consult my constrains with some experts. 3. Until now I have no idea about ORFS. 4. No have not tried, I am very glad it is possible. Once You have some spare time we could make a call. Regards

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