Can Genus and Innovus be used for Digital flow ins...
# ieee-sscs-dc-21q3
m
Can Genus and Innovus be used for Digital flow instead of openlane?
b
Yes, if this helps you and you have access to these tools. However, note that you still need to post all source files on GitHub to meet the contest guidelines.
• The project must be posted on a git-compatible repo and be publicly accessible. • The top-level of the project must include a license file for an approved open-source license agreement. Third-party source code must be identified and source code must contain proper headers.
m
Yes I have access to these tools. I am having problem with synthesize in openalne. It stops here:
26.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). terminate called after throwing an instance of 'std::length_error' what(): hash table exceeded maximum size. use a ILP64 abi for larger tables. Marked 1 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/register.v:14$10721 in module $paramod\register\WIDTH=s32'00000000000000000000000000011011. Marked 1 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/register.v:14$10719 in module $paramod\register\WIDTH=s32'00000000000000000000000000011000. Marked 1 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/register.v:14$10717 in module $paramod\register\WIDTH=s32'00000000000000000000000001000000. Marked 2 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/multiplier53Booth.v:41$7221 in module $paramod\multiplier53Booth\WIDTH=s32'00000000000000000000000000110101. Marked 2 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/alignShift.v:21$5676 in module alignShift. Marked 1 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/boothSel.v:21$10734 in module $paramod\boothSel\WIDTH=s32'00000000000000000000000000110101. Marked 1 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/register.v:14$10731 in module $paramod\register\WIDTH=s32'00000000000000000000000000000110. Marked 1 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/register.v:14$10729 in module $paramod\register\WIDTH=s32'00000000000000000000000011000000. Marked 1 switch rules as full_case in process $proc$/openLANE_flow/designs/fma/src/register.v:14$10727 in module $paramod\register\WIDTH=s32'00000000000000000000000101110111. [ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /openLANE_flow/designs/fma/runs/15-10_08-43/logs/synthesis/1-yosys.log |& tee >&@stdout" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child killed: SIGABRT [ERROR]: Please check yosys log file [ERROR]: Dumping to /openLANE_flow/designs/fma/runs/15-10_08-43/error.log [INFO]: Calculating Runtime From the Start... [INFO]: flow failed for fma/15-10_08-43 in 0h1m47s [INFO]: Generating Final Summary Report... [INFO]: Design Name: fma Run Directory: /openLANE_flow/designs/fma/runs/15-10_08-43 Source not found. ---------------------------------------- LVS Summary: Source: /openLANE_flow/designs/fma/runs/15-10_08-43/results/lvs/fma.lvs_parsed.gds.log Source not found. ---------------------------------------- Antenna Summary: No antenna report found. [INFO]: check full report here: /openLANE_flow/designs/fma/runs/15-10_08-43/reports/final_summary_report.csv [INFO]: Saving Runtime Environment [ERROR]: Flow Failed. while executing "try_catch [get_yosys_bin] -c $::env(SYNTH_SCRIPT) -l [index_file $::env(yosys_log_file_tag).log 0] |& tee $::env(TERMINAL_OUTPUT)" (procedure "run_yosys" line 34) invoked from within "run_yosys" (procedure "run_synthesis" line 10) invoked from within "[lindex $step_exe 0] [lindex $step_exe 1] " (procedure "run_non_interactive_mode" line 43) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "./flow.tcl" line 356)
While I was able to sythesize my design on genus using skywater_fd_hd lib files. but when I go to innovus and input the lef files. it gives errors about layers in the lef files.
Is there any way to use genus generated synthesis file in openlane and complete rest of the flow with openlane or otherwise correct the above error I am facing in openlane
@mehdi @Boris Murmann @Manar Abdelatty
b
@Muhammad Usman, have you looked at the flow used here? I think it is well documented. https://priyanka-raina.github.io/ee272b-spring2021/
m
@Muhammad Usman You should be able to run a design through openLANE with a genus synthesized netlist. what I see from your error is that you are running synthesis again with yosys. You should bypass it.