Hey All, [updated] So after running my verilog design code in openlane they generated a final_summary_report table with necessary information and the die area is showing 0.15618mm^2. Is this going to be the approx area of my design? If so then it's smaller than 7mm^2 so if anyone is interest in merging or needs home a home then let me know. I am already talking to the Egypt team. the github repo can be found here: https://github.com/omiya2106/DeepSAC things to be done: 1. running it in caravel and getting the wrapper testbench and layout files

Hi, great job! Please take care about timing You have a lot of violations !

any suggestion on how to take care of the timings? or what we usually do to maintain a good timing constrain?

in Your config file fo You provide timing constrains ?

i just setup something like this in config.tcl # User config set ::env(DESIGN_NAME) DeepSAC_sleep # Change if needed set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v] # Fill this # Fill this set ::env(CLOCK_TREE_SYNTH) 10.0 set ::env(CLOCK_PORT) "clk" set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl if { [file exists $filename] == 1} { source $filename }

ok, so if You want we can make a zoom and I will show You how to setup some constrains, I am not an expert however I have struggle a lot with that recently

that will be great! when are you free? let me know the time and your email and I'll send a zoom invite

okay give me 5 mins