Hello to all, I would like to consult some issues related to STA analysis, especially multi cycle paths. So I have prepared some test circuit on the RTL level then made logic synthesis and read it in OpenSTA (find attached all the source files). What occurs is that OpenSTA does not find the launch FF gives me some strange names of registers, nets ports, which seems to be not related to the GT netlist. Anybody willing to help ?

Hi @User, please take a look at the message below: A new channel named #timing-closure has been created to help people with timing issues. You might find some support there as well. https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1635276654053900

@User Thank You, I will take a look to the channel #timing-closure