Hey All,
when running my design through DRC and LV...
# ieee-sscs-dc-21q3o
Omiya Hassan
10/27/2021, 5:58 PMHey All,
when running my design through DRC and LVS they are showing I have 3 pin and 3 net violations and they are all antenna violations. Are there any tips or suggestions you can give to eliminate this problem?
the antenna report can be found: https://github.com/omiya2106/DeepSAC/tree/main/Caravel%20Hardening/openlane%20run/reports
s
Siva Prasad
10/28/2021, 8:36 AMHave you tried different Diode placing strategy ? If not try setting
DIODE_INSERTION_STRATEGY to 2 or 3.
Also increasing route iterations may reduce the violations.
o
Omiya Hassan
10/28/2021, 6:04 PMthank you alot @User I'll try it and let you know
Omiya Hassan
10/29/2021, 4:14 AMthanks again for the suggestions but I guess it was the clock period timing especially the static timing analysis that was generating the violations. I have corrected it and now have a clean flow.