@User: What you're showing in the screenshot is a DRC error, not a feedback error. Use "feedback find" to find the overlap errors.

@User I have not got your point about feedback error (what is feedback error?), kindly see the attached screenshot I have run the

feedback find

command and result displays:

There are no feedback areas right now

Oh, sorry, the overlap error is from DRC, not extraction, so the area shown is in fact the error. If you run the command "select area" followed by "what", it will tell you all the layers under the area inside the box, which should tell you which of the layers cannot be overlapped (e.g., metal5 cannot overlap metal5 resistor).

I have tried it, but still I am unable to find the cause of error, you may see in the attached screenshot. That there is only metal5 in the area and it should not cause a drc error, am I right?

Can you please post that layout?

Here I have attached the gds file

Looking at your layout, the probe cell is being connected to from the side by metal5. This is not a legal connection. The probe cell's top layer is metal5 on the bottom (i.e., Y-axis), with a narrow stripe of metal5 resistor above it, with another strip of metal5 above that, labeled "X". This configuration implies that connections should only be made at the top, connecting to the part labeled "X". By coming in from the side, the metal5 route is shorting across the resistor, which is what generates the DRC errors.

What is the function of probe cells? by looking its Verilog model, It seems to be some kind of buffer.

@User: This appears to be an error in the openlane setup. All cells with

probe

in the name should be in the

no_synth.cells

file. Probe cells are designed to bring an internal signal in a digital layout up to the top level where it can be connected to a pad for probing using a probe station. However, as indicated in the thread above, usage of the probe cell in synthesis is showing up an error in the OpenROAD router, as the router is shorting across the metal5 resistor in the probe cell and connecting to the internal net behind it.

@User They are part of the drc exclude list here https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/openlane/sky130_fd_sc_hd/drc_exclude.cells#L46 so openlane shouldn't use them in synthesis. @User Is the cell added by openlane directly after synthesis or a later step ?

Thank you @User That might not be an error in OpenLane, as my design was large enough for OpenLane to synthesis, it was giving errors about the the table size, and was recommending ILP64. So, I had used Genus for synthesis. The design is at final stage, and we have integrated our three designs in user wrapper and this is the only drc error, it is not feasible to resynthesize at this stage (I will have to repeat the whole backend flow again). However, we will try to fix it using magic at top level.

@User: Okay, thanks, sorry for the false alarm. @User: Yes, there should be no particular issue with having the probe cell used as a buffer as long as you fix the incorrect routes. Now that you know that the routes need to connect cleanly to just the part of the cell labeled "X" and cannot cross the thin line that marks the metal5 resistor, it should be straightforward to fix the DRC errors in magic or klayout.

Yes, sure thank you @User