open-source-silicon.dev

image.png

config.tcl

macro.cfg

user_project_wrapper.lvs.lef.log

Hello all,
During Integration of two Macros, I am getting LVS mismatch for about 250 nets. In the generated gds, the power pins of the Macros are not getting connected. When I enable FP_PDN_ENABLE_RAILS , I am getting illegal overlap errors. And when I disable the same, the power pins are not getting routed. Can somebody help on this issue?

```set ::env(GLB_RT_MAXLAYER) 4, the default value here is 5, ```


Is this warning significant? How should we remove this?

could you post the view of pdn only, there should be a def file in the results/placement folder

Thanks <@U01GLU3UDRD>, I'll try once without defining any standard cells in the wrapper module and update you.

ok, check out if veriical power straps of the macro connects to the horizontal one of the wrapper

you should see some vias on the crossings, remember that the groups of horizontal straps are 4 supply voltages and 4 grounds

<@U01GLU3UDRD>: Yes there are some vias on the crossings of the Horizontal and vertical straps in the Macro

I checked by removing all the standard cells from the wrapper module but still I get the LVS errors

I used Diode insertion, so will this be considered as Standard cells in the wrapper?

Because all the mismatch nets are the power and gnd pins of sky130_fd_sc_hd_diode_2

<@U01GLU3UDRD>: The problem was with diode matching only. Now I am getting certain mismatched pins. Except for the power and gnd pins, I haven't connected the other pins anywhere

<@U02A70RDME3>:  The idea is that you start with the empty user wrapper layout, because that has all the pins defined and positioned on the boundary where they connect.  Because it's a wrapper that drops into a predetermined place, it defines all the pins that are possible to connect to, whether or not you actually connect to them.  So you need to keep those pins in the layout.