Hello all. I have instantiated an analog module wh...
# ieee-sscs-dc-21q3
r
Hello all. I have instantiated an analog module which I have layed out in hand using magic. While doing so I had no DRC errors (a picture of tkcon window is shown below). I placed the analog macro in wrapper and ran the openlane flow where at the end I get around 440 errors a picture of which is also provided. FYI I am using the recent version of magic. So can I ignore the error that is shown by openlane? Thank you in advance.
m
What is the error flagged by openlane?
r
It shows total number of violations is 440. @User. Isn't that an error?
m
I meant the details of the error? did it dump a report?
r
After the error it displayed flow failed but the flow completed. It didn't dump any report. Is that what you are asking @User?
m
there should be a DRC summary somewhere? it looks from the screenshot that you might have some unconnected wells.
r
This is the log file that got generated.
@User @User any advice?
m
I would let Tim weigh in here. There aren't much detail in this log file
r
Thank you @User
@User @User When I use the extract command I am getting around 2600 warnings as shown in the figure below. Is that the cause of this error? Thank you in advance.
t
No, those are just normal warnings about source-drain tied transistors (which are perfectly fine)..
The DRC error message says that you have N-wells that are not tied to anything.
r
@User I have placed substrate contacts in the nwell region and have connected them to VDD metal line. What else must be done to avoid this error message?