Hey all, So the USA2 and EGYPT team successfully merged their designs in user_project_wrapper and generated gds file with no DRC errors. Could someone show me what I need to do next? and what needs to be submitted to the mpw-precheck?

follow the directions at https://github.com/efabless/mpw_precheck.

@User thanks! @User in submitting the job to the mpw-precheck platform through efabless. what necessary files should be in our git repo? i dont want to miss out anything on the checklist this is the current state of our repo: https://github.com/omiya2106/SSCS_PICO_chip5

Your final gds file and the top module inside it should be named user_project_wrapper.

@User please check the complete directory structure for the project. https://github.com/efabless/caravel_user_project/blob/main/docs/source/index.rst#checklist-for-open-mpw-submission

@User could you check our chip5 repo and see if the checklist is done https://github.com/efabless/caravel_user_project/blob/main/docs/source/index.rst#checklist-for-open-mpw-submission provided by jeff. And then submit it for the mpw precheck in efabless website? Through my job > submit mpw? It takes sometime and I wanted another hand from the team to see if im doing something wrong.

I used caravan for the integration. For the digital module (top) I added

Xtop <pins> top

in the spice file and consistency check was cleared. In the info.yaml I gave

user_analog_wrapper.spice

file. Consistency check probably checks module only at top level. You can probably do the similar thing with Top verilog wrapper. try instantiating analog module as

AnalogMod myMod(pin1,pin2,pin3.....);

.Though the efabless people can tell more