For the problem mentioned above I have opened the ...
# ieee-sscs-dc-21q3
r
For the problem mentioned above I have opened the gds file using klayout and tried to look at the position of errors. One of the errors mentioned above as capm.2b (for the cell mim_cap_3) is due to the violation of "minimum spacing between the m3 bottom plates <1.2 um". I could see in both the magic file of the analog macro and the generated GDS file of the wrapper this constraint is satisfied. Whereas when the gds file is viewed using "view-job-errors --design_path ." , this violation seems to appear. How could this be solved? The snapshots of the gds file of the wrapper(slack1.png) and when viewed using "view-job-errors --design_path ." (slack2.png) is attached for reference below. Thank you in advance.
r
I am pretty sure mim cap bottom plate distance DRC error is flagged in magic because I encountered some while laying out my analog circuit. Are you running drc with
drc style drc(full)
in magic?
r
yes @User.
r
can you point me to your git link? I will see if i can find something
r
l
Now I see it... Magic doesn't flag it for me. Strangely, it doesn't show any errors while running the efabless MPW precheck, but KLayout does.