@User: Tell me what worked and what didn't. In spite of our fix for timing errors within the management SoC, which appears to be fully working, there are some timing issues in a few modules outside of the processor. One of those problems shows up in the serial shift register loader for the GPIOs on the right side of the chip (GPIO 0 to 18, or 13 in the case of the Caravan chip). I'm not sure what version of the "blink" test is being shipped with the boards right now. If it's the one that drives the UART to display "Hello!" to a 9600 baud LCD display, then it is writing values to the GPIO configuration registers on the right side that probably do look unusual. They are compensating for a "bit slippage" along the chain. The evidence is that there is a one-bit shift per GPIO, so the values have to be shifted in the configuration registers to compensate. I have not entirely confirmed this, since the board I was testing with stopped working due to reworking solder jobs on the board too many times. I'm currently waiting on another board being shipped to me, which got stuck in Memphis for several days; it should be arriving today, so I can get back to figuring out the bit positions in the configuration registers. Like all timing violations, it could vary from chip to chip based on the position of the chip on the wafer. I have so far only looked at one chip, so I don't have much statistical variation from that (!). it's possible that you may not observe a timing violation at all. At any rate, I'm here to help answer any questions and get you testing your design.

I was uploading this program: https://github.com/efabless/caravel_board/blob/main/firmware/blink/blink.c