I am facing this problem after the command of

make user_project_wrapper

for top-level integrationmake -C openlane user_project_wrapper make[1]: Entering directory '/home/shahid/caravel_user_project/openlane' Makefile:46: warning: undefined variable 'MCW_ROOT' # user_project_wrapper mkdir -p ./user_project_wrapper/runs/22_08_17_19_46 rm -rf ./user_project_wrapper/runs/user_project_wrapper ln -s $(realpath ./user_project_wrapper/runs/22_08_17_19_46) ./user_project_wrapper/runs/user_project_wrapper docker run -it -v $(realpath /home/shahid/caravel_user_project/..):$(realpath /home/shahid/caravel_user_project/..) -v /home/shahid/OSPDKs:/home/shahid/OSPDKs -v /home/shahid/caravel_user_project/caravel:/home/shahid/caravel_user_project/caravel -v /home/shahid/Openlane:/openlane -e PDK_ROOT=/home/shahid/OSPDKs -e PDK=sky130B -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/home/shahid/caravel_user_project/caravel -e OPENLANE_RUN_TAG=22_08_17_19_46 -u 1000:1000 \ efabless/openlane:2022.07.02_01.38.08 sh -c "flow.tcl -design $(realpath ./user_project_wrapper) -save_path $(realpath ..) -save -tag 22_08_17_19_46 -overwrite" [INFO]: _ __ _ __ _ __ __ _ / \ | \ / _]| \ | | / || \ / _] | | | o ) [_ | _ || | | o || _ | / [_ | O | | _/ _]| | || |___ | || | || _] | | | | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____| [INFO]: Version: 2021.11.23_01.42.34 [WARNING]: The version of open_pdks installed does not match the one required by the OpenLane flow scripts (installed: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70, expected: c5730b574461889c82858b08d12ba42423d9c2cb) You may want to re-install the PDK by invoking

make pdk

. Tool vlog2Verilog is required by the flow scripts being used, but appears to not be installed in the environment. Tool drcu is required by the flow scripts being used, but appears to not be installed in the environment. Tool cugr is required by the flow scripts being used, but appears to not be installed in the environment. Tool klayout is installed in the environment, but has no corresponding entry in the flow scripts. Tool vlogtoverilog is installed in the environment, but has no corresponding entry in the flow scripts. Tool git is installed in the environment, but has no corresponding entry in the flow scripts. The version of cvc installed in the environment does not match the one required by the OpenLane flow scripts (installed: d172016a791af3089b28070d80ad92bdfef9c585, expected: 90e78b4598c1f5c35fcc3b8fc4d80fde7c881445) The version of magic installed in the environment does not match the one required by the OpenLane flow scripts (installed: 085131b090cb511d785baf52a10cf6df8a657d44, expected: 0bb6ac1fa98b5371c73156b6e876925397fb7cbc) The version of netgen installed in the environment does not match the one required by the OpenLane flow scripts (installed: bfb01e032f668c09ff43e889f35d611ef0e4a317, expected: 738c1f7b3705bca2f1cc66fbc1cfb20f12d49a06) The version of yosys installed in the environment does not match the one required by the OpenLane flow scripts (installed: cfe940a98b08f1a5d08fb44427db155ba1f18b62, expected: d061b0e41a2023b5e72794563b94d6a9b5ab41a1) The version of openroad_app installed in the environment does not match the one required by the OpenLane flow scripts (installed: 0b8b7ae255f8fbbbefa57d443949b84e73eed757, expected: b79f266fe41540eabc064bcaddfe19ed715ac5c2) [WARNING]: OpenLane may not function properly. [INFO]: Running non-interactively [INFO]: Using design configuration at /home/shahid/caravel_user_project/openlane/user_project_wrapper/config.tcl [INFO]: Sourcing Configurations from /home/shahid/caravel_user_project/openlane/user_project_wrapper/config.tcl [INFO]: PDKs root directory: /home/shahid/OSPDKs [INFO]: PDK: sky130A [INFO]: Setting PDKPATH to /home/shahid/OSPDKs/sky130A [INFO]: Standard Cell Library: sky130_fd_sc_hd [INFO]: Optimization Standard Cell Library is set to: sky130_fd_sc_hd [INFO]: Sourcing Configurations from /home/shahid/caravel_user_project/openlane/user_project_wrapper/config.tcl [WARNING]: Removing exisiting run /home/shahid/caravel_user_project/openlane/user_project_wrapper/runs/22_08_17_19_46 couldn't write file "/home/shahid/caravel_user_project/openlane/user_project_wrapper/runs/22_08_17_19_46/logs/flow_summary.log": no such file or directory while executing "exec echo $message >> $::env(LOG_DIR)/flow_summary.log" (procedure "puts_warn" line 5) invoked from within "puts_warn "Removing exisiting run $::env(RUN_DIR)"" (procedure "prep" line 180) invoked from within "prep {*}$args" (procedure "run_non_interactive_mode" line 14) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "/openlane/flow.tcl" line 356) make[1]: * [Makefile:72: user_project_wrapper] Error 1 make[1]: Leaving directory '/home/shahid/caravel_user_project/openlane' make: * [Makefile:73: user_project_wrapper] Error 2

Hi, Does anyone know what we receive in the MPW7 in case of being accepted? the board that is in the documentation with the integrated circuits, or just the integrated circuit? what will we get in the end?

what is the size of external flash on the caravel board?

Where is the MPW-2 caravel PCB layout details ? I see too many folder under https://github.com/efabless/caravel_board/tree/main/hardware

Waiting on @jeffdi to clarify

see the README in the caravel_board repo… https://github.com/efabless/caravel_board/blob/main/README.md

hardware/caravel_breakout_v2

Hi @Matt Venn, in caravel chip what is the max clock frequency the user area can get from the wishbone bus available to user area?? Any idea?

image.png

sorry for missing the update

deleted the tweet that posted the flipped one and posted a new one

Hi everyone! I'm trying to program my MPW2-board GPIOs. I have done what is in https://github.com/efabless/caravel_board/blob/main/README.md: after installing the toolchain I tried pip3 install pyftdi, cd firmware/blink, make clean flash, but the make statement gives an error like ".*orig can´t be read*". So, I've tried to manually program the board by mean of the caravel_hkflash.py blink.hex statement, but it retrieves mfg=ffff, product=ff, project ID=ffffffff, and the board remains with the same blinking program as when it is powered on. Any ideas? Thank you in advance!

they already ship MP2-boards?

They ship me one because it was part of a Chip Ignite shuttle.

oh, ok, good luck with testing

Thanks!

Is there anything wrong with bypassing the mprj_io[6]_ser___tx connection and treating it the same as the other gpio ports? For context, we are designing our own custom test-board and I realized that I connected an important digital signal to io_in[6]. We won't really be using the RISC-V CPU but might need it to enable the gpio ports as user inputs. Will bypassing the UART affect our ability to configure the gpio ports?

Just to confirm, for connecting the caravel breakout board to the caravel hat board, we need to solder the connections right ?

I tried running the diagnostic on the nucleo board but got the following error saying mpremote not found, even though the python installation seems to work correctly. @mehdi

@Tim Edwards @jeffdi @Matt Venn I have a few MPW1 Chips with me and to test them I am trying out something different as I could not get hold of an FT232H Ic for USB to SPI. Following the caravel_pcb_v4_FTDI board I have connected the required 3.3v and1.8v LDO and 10 Mhz clock along with the reset button. Further I have connected an W25Q32 SPI flash to the QSPI Flash interface and am writing to the external flash memory using an Arduino. If my understanding is correct, on boot the Caravel will start reading from the flash memory and execute it in the management core. Currently my goal is to just get the management GPIO to blink an led and hence, I have used the /caravel_board/firmware/blink2/blink2.hex file. I just want to confirm : 1. If the steps that I have carried out make sense and is a feasible solution.

@Tim Edwards @jeffdi @Matt Venn I have a few MPW1 Chips with me and to test them I am trying out something different as I could not get hold of an FT232H IC for USB to SPI. Following the caravel_pcb_v4_FTDI board I have connected the required 3.3v and 1.8v LDO and 10 Mhz clock along with the reset button. Further I have connected an W25Q32 SPI flash to the QSPI Flash interface and am writing to the external flash memory using an Arduino. If my understanding is correct, on boot the Caravel will start reading from the flash memory and execute it in the management RISCV core. Currently my goal is to just get the management GPIO to blink an led and hence, I have used the /caravel_board/firmware/blink2/blink2.hex file. I just want to confirm : 1. If the steps that I have carried out make sense and is a feasible solution? 2. I have attached a screenshot of how the memory map looks like for the above mentioned hex file and if I have written it at the correct starting address( starting from the 4th byte ) and followed the right endianness. I apologise if I haven't explained it properly and thanks for the help.

I have a doubt regarding the Cravavel Datasheet, • Pg 12 for QSPI mentions the pins as D10,D9,D8,C10 which are labels for flash on Pg3 and are mostly missing on Pg4 • Pg3 mentions E3,E4,F4,F5 as flash2 SPI pins and Pg4 labels them for flash, flash2 and user area QSPI There seems to be some mismatch or please correct me if I have made an error reading the datasheet.

Following the previous queries, the external SPI FLASH (W25D32) with the data written at location 0x000, should be connected to D10,D9,D8,C10 or E3,E4,F4,F5 ?

Hi, the other day I received the MPW2 chips and board, and I went over the manual to do the initial IO test. Unfortunately got an "name too long" error and nothing happens. So I try to re-flash the nucleo board again just in case anything is out of date (model F746ZG), I manage to do the flash, but when finish the copy of the micropython files and the "config_io_o.hex", the nucleo board restarts and I got a fail.txt file that states that the format is incorrect, and seems to be related to the .hex file. Any idea how to fix that and manage to do the IO test? @Tim Edwards

Hi, guys I am new for design, I want to ask what are the difference between MPW 1-8?

Based on my understanding the final board has a management area and a user project area. I put the image below. I don't know whether it is correct or not. But here is my question: 1. What does the final PCB look like (or what physical board we can get ), could you give me the image of the physic board and circuit diagram and specification? (or you can give me the resource that I can find by myself). 2. How do each component in the management area connect to each other and connect to the user area? 3. How can I test the final physical board to check if each component is working well? And if something wrong , how can I find which part of the board needs to be fixed?

Hi, from the website below, the massage I got is we can only get daughter board back from the project and we need to design our own carrier board, is that true or not? https://github.com/efabless/caravel_board/blob/main/docs/Caravel_Board_Specs%20_clean.pdf

Along those lines I have a question about the PCBs as well. So will all of the components that each of the boards need already be soldered onto the boards when we get them? We don't have to purchase any of the components ourselves or solder any of them?

For the nucleo board, how could we evaluate and test the board to make sure that the board is work well and show correct output value?

what vendor was used for the WLCSP breakout boards for MPW 2/3? The quality feels quite a bit better than the ones from MPW1. (Trying to get some more breakouts made so I don't have to keep using the MPW1 ones)