Ok so i'm seeing some slightly confusing results. Is there a timing diagram somewhere for the intended phase relationship of the clock to data, and expected setup/hold margins etc?
m
Matthew Guthaus
12/09/2021, 3:05 AM
The delay outputs are related to the negative edge so that is important. Setup and hold of inputs are relative to the positive edge.
Matthew Guthaus
12/09/2021, 3:06 AM
I was measuring the setup time and it was on the order of 0.5ns unfortunately. There's a big buffer driving the flops.