but it looks like the clock-to-out delay here is massive and huge read capture delays greatly improve performance

The output of the SRAM is a pretty tiny buffer, so I'm curious what was added before the IO buffers. I'll have to check that out in the design.

This chip was done before we had the capability in OpenROAD to do timing analysis at the top level, so I assume that the tiny output buffers are directly driving the pad inputs, and probably through long wires to boot. That would not be realistic for an SRAM used as a macro inside a project.

Well, the good news is once this data has been collected, it's going to be straightforward to repeat for additional test chips