@User As we already discussed briefly on a chat I did commit a IO test design for MPW4. (I hope it gets through as there seem to be magic problems ATM). The project is https://efabless.com/projects/621 and the gds is in the repo as gds/user_analog_project_wrapper.gds.gz. I think there are some interesting characterisation 'opportunities' when looking at IO cells. Next to the electrical performance of the cells (e.g. delay, threshold, etc...) one can also look at latch-up behaviour and ESD performance. @User Is there a gds with the RDL layer design somewhere ? I do find a gds with the bond pad location in the caravel repo but I don't seem to find the RDL design.

It's not part of the design we send to SkyWater, so you will need to go back to the original repository, which has now been relabeled

caravel_mpw-one

, and find

gds/caravel_bump_bond.gds

.

It would be interesting to do S-parameter extraction on the RDL so we can characterize the I/O cells more accurately. Although at these speeds I'm not sure how much of an impact it will have.

I agree that high-frequency effects are not the first focus. From the other side I mainly have experience with wire bonded chips and there the self inductance of the bond wires has a non-negligible effect. My main target would be get a better view on actual signal seen on the core 1.8V signals of the IO cells that are connected out through RDL etc. E.g. is there overshoot expected etc.

Well you can extract s-params down to pretty low frequencies (kHz). We can also extract DC RLCs from the RDL too. In any case, let me know when the test chip is ready and we'll move from there.

@FatsieFS: The RDL layer:purpose assignments are a completely different mapping than what's in the SkyWater sky130 technology, and the vendor (Micross) didn't even provide a mapping, so it's all pretty ad hoc. There is a separate tech file for magic that can be found in the open_pdks installation under

sky130A/libs.tech/magic/bump_bond_generator/micross.tech

. The regular

sky130A.tech

tech file supports only the RDL layer, mainly just for reference. I'm not sure any of those layer mappings were implemented in the klayout decks.