If we really wanted a worst case retention test we could figure out the natural powerup state of each cell and use the complement of this as a test pattern

This is what I was thinking too. One thing I was curious about, with the current test procedure, is how coverage is guaranteed in the cells that aren’t symmetrical. For example the cells on the edge of the RAM that don’t have a neighbor. But I also get there is a limited amount of time you can spend on developing the test and looking at retention over space could be time consuming.

Internally I collect the test data as a bitmask of erroneous bits for each memory address