(<@U0175T39732> I'm still waiting on layout inform...
# silicon-validationa
Andrew Zonenberg
01/06/2022, 5:47 AM(@User I'm still waiting on layout information from you as input to this process)
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Matthew Guthaus
01/06/2022, 2:09 PMYes, classes just started at I've been sidetracked a bit...
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Andrew Zonenberg
01/06/2022, 3:06 PMSilly students getting in the way of research :P
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Matthew Guthaus
01/06/2022, 7:24 PMOk, just confirmed the layout:
The addresses go from the bottom to the top and there is a two-way column mux -- two 32-bit words per row. The array is 64 bits wide and 128 bits tall. So, the bottom row will have addresses 00 and 01 with the 32-bits interleaved starting with bit 0. If I use AA_B as the syntax for the address (A) and big (B):
Copy code
FE/FF: FE_0 FF_0 FE_1 FF_1 ... FE_30 FF_30 FE_31 FF_31
FC/FD: FC_0 FD_0 FC_1 FD_1 ... FC_30 FD_30 FC_31 FD_31
...
00/01: 00_0 01_0 00_1 01_1 ... 00_30 01_30 00_31 00_31
00/01: 00_0 01_0 00_1 01_1 ... 00_30 01_30 00_31 00_31