First off, frequency vs voltage shmoo at 10ns read capture delay

May I kindly ask. When you talk about frequency, you assume that a) the output line behaves like in a wave-pipelined fashion- And that b) the failure is not due to a potentially low slope of the nets on the output line. Thanks in advance.

I'm sampling the outputs with FPGA digital input pins. The output buffer should have ~the same slew regardless of what's going on in the core clock domain since I'm keeping the I/O power at a constant 3.3V

If I understand it correctly, the SRAM outputs are buf_8, and in this case, we have a relative high net capacity. This can be seen as an on-chip RC element. So I was just wondering, if the shmoo plot actually shows the transmission characteristics of that filter and conclusions on Fmax of the memory should be worth thinking about. It’s tough to measure dynamic behavior with such a filter in-between. But I might think completely bogus here again. Sorry for that.

For the time being I'm operating under the assumption that these results are lower bounds on performance, but that no further conclusions on actual performance should be drawn until the next test chip

Thank you for your reply. That's good to know, because I expect (hope) the Fmax of the memory itself to be much higher. Cheers, Tobias