@User I have reached the point where I am working on integration (yay!). I have a questions about the analog project wrapper: There are two analog pins on the standard I/O cells: gpio_analog, and gpio_noesd. I assume that corresponds to pad_a_esd_0_h and pad_a_noesd_h? What are the voltages of the I/O clamps? I am not finding many details on them. My power rail is going to to be in the range of ~2 - 5V so I assume I want to tie io_clamp_high to the pin input (or do I ground it?) and float io_clamp_low? do we need to do anything with unused digital signals intended to be driven by the project? Tie them low? I have a enable pin that enables my switching stage that I was intending to drive through the digital input. Things could get sad if that gets enabled at the wrong time. Is there some default state or anything before the I/O gets configured?

(1) Yes, the gpio_analog is connected to pad_a_esd_0_h and gpio_noesd is connected to pad_a_noesd_h. (2) I assume you mean the 3 clamps that have connections into the analog project wrapper. These are all high-voltage clamps. You want to connect the high side to the power supply and the low side to ground (ground return for your circuit, although you can also use VSSIO or VSSA, although you'd want to be careful about how much of a ground loop you're creating that way). (3) I have reworked the digital buffering between the management SoC and the user project area so that you can just leave unused digital lines floating. (4) In the initial state, every pad is configured for management control, but the input buffer is enabled, so as long as the user power supply is up, then the value at the pin will be seen at the user input (a.k.a. "io_in" and "io_in_3v3"). So as long as you are asserting the correct value off-chip, you should be fine.