In particular, I am trying to understand if there is a difference between vdda1 and vdda2. And why there are 18 gpio_analog ports but 27 io_in ports on the xschem harness

There was a nice PDF file but somebody opted to convert everything to Sphinx. I will post the original PDF. There are 18 GPIO analog ports because connecting a user area signal directly to the GPIO pad bypasses everything and can be disruptive to any signal that is required for use by the management SoC. There are a handful of signals (the ones closest to the management SoC) that are "reserved" for use as UART Tx/Rx, secondary SPI flash, SPI, etc. Given the unlikelihood that somebody would need 38 connections directly to the pad, the reserved ports are prohibited from having direct connections so that the user project area cannot accidentally disrupt the operation of the management SoC by forcing a value on one of those pins. As for vdda1/vdda2: The user area was divided into left and right sides, and the power domains were split. This allows a user project to have two independent voltage domains (four, if you include the vccd1 and vccd2 1.8V domains). If you do not need multiple independent voltage domains, you can just connect them together internally (or externally) so you can double the maximum current you can inject through them.

So (27 - 18) io_in ports are shared with functionality between the management SOC? Or is that another set of pins entirely?

All GPIO are shared with management, but a handful of them have dedicated functions unrelated to the simple GPIO read/write functions: 0 = JTAG (currently unused) 1 = SDO 2 = SDI 3 = CSB 4 = SCK 5 = ser_rx 6 = ser_tx 36 = flash_io_2 37 = flash_io_3 There are other functions on other pins but none of them is critical to the operation of the management SoC. In theory, you can use all of them---that's why they are all GPIOs---but tying something directly to the pad will block the function for the management SoC; or worse, tying something to flash_io_2/3 is likely to kill the SPI flash chip, and tying something to CSB might randomly cause the chip to reset.

Wait, I am still confused. There are 38 IO pins. but 27 IO ports broken out to the carval user area. Thats implies that none of the dual function pins are accessable from carvan.

Analog pins are connected to absolutely nothing but a named pin on the analog user wrapper. There are 38 I/O pins total on the padframe that are available to the user space. On caravan, 11 are analog only, and the other 27 are GPIO. Of the 27 GPIO pins, 18 can be used as analog if all the digital functions are shut down, and the other nine (the ones I listed above) don't expose the analog connection to the user project area, so you don't have a way to access them except through the normal digital pins.

Ah, I see. I was also forgetting to subtract out the new pads that are analog only. Thanks for the clarification!