Here are the extracted and schematic netlists
# caravan
w
Here are the extracted and schematic netlists
t
Thanks. Let me know if you have any issues with netgen 1.5.185. I think it should be good.
I think I have a good idea what happened with the last modification. Now that the flattening routine is handling parallel devices, it needs to recognize the special kind of parallel device that has unconnected pins. If it doesn't, the unconnected pins get merged together by the flattening, which would explain what you're seeing in the output.
If you can post the layout-extracted netlist as opposed to the layout, that would be helpful.
w
Oh whoops, my bad
user_analog_project_wrapper.spice
t
Thanks!
The error turned out not to be as bad as I thought. I'm not sure why it appeared all of a sudden, because the code has been wrong from a number of commits back. It is just a mishandling of checking a flag bit which is causing extra error messages to be printed for something that is not an error. When I cleaned that up (just pushed to opencircuitdesign.com) and re-ran on your example above, all the weird error messages go away, leaving a single property error which reflects the difference in decap cell count in the "cascode_bias" cell.
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