Hi, everyone I would like to connect several(around 10) LDOs to the user_wrapper of the caravan and I have several questions. 1. Each ldo has 23 inputs and 10 outputs. (All of them are digital and needs 3.3V IO)  Only one ldo will be tested at a time. I am not sure what is the easiest solution to connect these pins to the wrapper.  (Maybe I should use SPI or some other method?) 2. For the above digital signals, should I connect them with io_in_3v3[0 - 26] and io_out[0 - 26] pins on the user_wrapper? (Want to make sure these inouts support 3.3v) 3. It seems that openlane is a good choice to connect my ldos with the wrapper pins. But for now I know nothing about the openlane. Is there any example or tutorial may be useful for me? Thanks!

The

io_out

signals do not support 3.3V. You will need to have a level-shift-down circuit, which you can use from the HVL library (

hv2lv

) or just use an HVL buffer with the power supply tied to 1.8V (the inputs will be 3.3V tolerant). On the

caravan

design, see the file

verilog/rtl/user_analog_proj_example.v

in the

caravel_user_project_analog

repository. This has a complete description of the pin mapping. Avoid using

mprj_io[4:1]

except as a last resort, as they are used by the housekeeping SPI, and using them for projects requires making sure that the FTDI chip on the development board is not driving those pins. But they can be used if you need them. Just remember that you have the entire SoC and logic analyzer at your disposal, so I would expect that it is more convenient to drive all of the LDO inputs internally through the wishbone bus (although those are 1.8V signals, so you would need to use the HVL library

lv2hv

level shifter to get signals up to 3.3V).

Thank you for your reply. Could you make a brief explanation of the difference among fishbone bus, logic analyzer and io ?