In the checklist I've just seen "The hardened Macros are LVS and DRC clean" Does that mean for an analogue design, an xschem schematic is a requirement? I just typed transistor W/L into ngspice to run my sims 😅

At the moment, no schematic is required for analog designs, although we are considering whether to make that a requirement or not. Automatic DRC is run on everything. LVS is only run by the synthesis tools on digital designs. If you want to ensure that your analog design works, running LVS and simulating with an extracted post-layout netlist are crucial.

Thanks for clearing that up 🙂 I'm a beginner so going for very basic stuff, atm just a single comparator so I've run the extracted layout through sim. I think I'll get my repo to the bare minimum level of passing the checks then think about making an xschem schematic too. On a related note: Are we allowed to use the SONOS devices (which I see are available in the magic device generator), or is that gonna add extra masks to the shuttle? I was thinking of dropping a few in one corner of the chip just to characterise them a bit.