Can somebody help me? I am trying to use OpenLane to harden my analog project. I am using Caravan. I cloned the analog user project but have no idea how to run openlane to create my top level .gds. It seems running make user_analog_project_wrapper does not give any results, as it states that this makefile target is not found. The reason I want to use OpenLane is I want to place my Analog I/O cells which connect to pads and connect the Analog I/O cells' digital I/O to some standard cells.

This is a different use-case than the digital synthesis with Openlane; you need to first create macro blocks of the analog cells (LEF, liberty, verilog, and GDS views), and then set up Openlane to tell it where to place the macros and how to do the routing from the macros out to the wrapper pins. However, generally speaking, analog projects have important constraints on the width and positioning of analog signal and power routes that are difficult to specify for a digital router. If the design is mixed-signal and has a large digital component, then this setup may be worth the trouble of doing. Otherwise, if it is purely analog or has only small digital blocks with a limited number of digital signal wires, then it's a lot easier just to route the whole thing by hand. But if you want to do it with Openlane, then please ask in the #openlane channel if you don't get a response here. For starters, this would work much like the chip top level routing found in caravel and caravan, so the setup file would look something like

caravel/openlane/caravel/config.tcl

, which is all routed at the level of macros.

Hi @Arman Avetisyan, I was wondering if you had any luck using OpenLane with Caravan. We're facing a similar issue, we had to switch and use Caravan due to sharing purposes, and given that our design relies more or less heavily on the RISC-V SoC, the manual routing of the macros it's a bit off the table.

I just made a wrapper def file with pins and placed it in caravan gds manually and routed it manually. Looking back it was terrible idea because I know that I have timing violations between the digital part and the connections to GPIO

Thank you @Arman Avetisyan for your answer. Not the news I wanted to hear, we'll try to find a workaround. Good job on your documentations by the way!

one small note: Router/Magic respects Non default rules in the DEF file