What part of esd protection is the user project area responsible for?

Back to your diagram: The 11 analog pads on the Caravel chip do not have the diodes

SDp

and

SDn

. The reason is that analog designs often need either (1) a high voltage supply which would forward-bias into the power supply if

SDp

were present, (2) a negative voltage supply which would forward-bias into the ground supply if

SDn

were present, or (3) a very high-speed input or output which would fail to meet bandwidth requirements if the diode capacitance is present. In the case that your analog signal is not high voltage, negative voltage, or faster than 50MHz, you should be using the existing GPIO pads for your analog signals. Otherwise, you need to implement the diodes in some fashion, or accept the risk of a very ESD-sensitive device. The preferable solution is to have a pair of diodes as close to the pad as possible and some series resistance between the pad and circuit. Again, because the circuitry is limited to the user area, you can get a diode only so close to the pad (about 200um), which is not ideal ESD protection but is much better than having no protection.

Thank you! This is super helpful. Our design will be using a "special power supply" so I think I understand you instructions for connecting the clamps in that case. We will also have analog IO at that voltage. So I will plan on adding diodes for those signals. Just to make sure I understand, I created a diagram of those connections which I hope accomplishes these two things. Does it look right?

The power-on-reset is connected into a power supply, not a signal pad, so it is a bit different. All the pads (or almost all) on caravel are GPIO pads, and the diodes are formed just using the diffusion of the transistors in the output buffer stage. You have several choices, but using magic, under the "Devices 1" menu, choose "ndiode" or "pdiode", and then select the 11V (that's breakdown voltage) diodes, P and N. My advice on sizing is to look at the GPIO pads and find the transistors under the pad, and figure out how much diffusion area they have in total on the output side of the gate. That would be the equivalent diffusion area for a diode that probably meets either 4000 or 8000V HBM (human body model) ESD events. That is also probably what limits the GPIO pads to 50MHz. You can get away with a quarter of that amount of diffusion, and you'll have a slightly-ESD-sensitive part (i.e., about 1000V HBM), but without simulation I can't tell you how much bandwidth you'll gain by that.